OpenLane

Category

FPGA / HDL / VLSI / Architecture

Provider

OpenLane

Type

docs

Level

Advanced

Topic

FPGA / HDL / VLSI / Architecture

Track

FPGA / HDL / VLSI / Architecture

Section

Learning path

Format

Documentation

Status

publishable

Commercial

candidate

Featured

no

Fast start

no

Sequence

8.0

Priority

Standard

Primary source

direct_links_master

Sources

direct_links_master, mega_open_hub

ID

f1788a21bc28076f

OpenLane 2 Docs

OpenLane

Flow docs for reproducible open ASIC implementation with configurable steps and tooling.

Yosys

YosysHQ

The core open synthesis tool for serious FPGA and ASIC experimentation.

Verilator + cocotb bundle

Verilator / cocotb

Gives you modern simulation and Python-based verification habits.

OpenROAD

OpenROAD Project

Critical open path into physical design and full RTL-to-GDS workflows.

OpenTitan + Chisel bundle

lowRISC / Chisel

Great long-term contributor target once you are comfortable with verification and hardware architecture.

Project F

Project F

Clear practical tutorials for FPGA graphics, timing, and hardware thinking.

Nand2Tetris

Nand2Tetris

One of the best bottom-up systems courses ever made.

MIT 6.004 / Computation Structures

MIT

Bridges digital logic, computer architecture, performance, and systems reasoning.

HDLBits

HDLBits

Fastest hands-on path to becoming comfortable with HDL syntax and design patterns.

Nandland

Nandland

Beginner-friendly FPGA and HDL videos.

Project F videos

Project F

Visual, practical FPGA project walkthroughs.

OpenTitan Docs

lowRISC

Open-source silicon root of trust project with hardware, software, and documentation for secure silicon contribution.