AI Power Progress iA
Category
FPGA / HDL / VLSI / Architecture
Resource detail
Yosys
The core open synthesis tool for serious FPGA and ASIC experimentation.
architecture build docs documentation fpga hdl intermediate learning-paths synthesis-tool-docs tool vlsi yosyshq
Resource Metadata
Provider
YosysHQ
Type
docs
Level
Build
Topic
FPGA / HDL / VLSI / Architecture
Track
FPGA / HDL / VLSI / Architecture
Section
Learning path
Format
Documentation
Status
publishable
Commercial
candidate
Featured
yes
Fast start
yes
Sequence
6.0
Priority
Fast
Primary source
direct_links_master
Sources
direct_links_master, mega_open_hub
ID
1950d2bbab9f7403