OpenLane 2 Docs

Category

FPGA / HDL / VLSI / Architecture

Provider

OpenLane

Type

docs

Level

Advanced

Topic

FPGA / HDL / VLSI / Architecture

Track

FPGA / HDL / VLSI / Architecture

Section

Learning path

Format

Documentation

Status

publishable

Commercial

link-only

Featured

no

Fast start

no

Sequence

nan

Priority

A

Primary source

mega_open_hub

Sources

mega_open_hub

ID

670375d60ea38731

OpenLane

OpenLane

Best structured on-ramp into reproducible open-source ASIC flows.

OpenTitan Docs

lowRISC

Open-source silicon root of trust project with hardware, software, and documentation for secure silicon contribution.

cocotb Docs

cocotb

Python-based testbench framework docs for HDL verification.

Yosys

YosysHQ

The core open synthesis tool for serious FPGA and ASIC experimentation.

OpenROAD

OpenROAD Project

Critical open path into physical design and full RTL-to-GDS workflows.

Verilator + cocotb bundle

Verilator / cocotb

Gives you modern simulation and Python-based verification habits.

OpenTitan + Chisel bundle

lowRISC / Chisel

Great long-term contributor target once you are comfortable with verification and hardware architecture.

Python Docs

Python

Canonical language docs for core syntax, standard library, packaging, and advanced topics.

Project F

Project F

Clear practical tutorials for FPGA graphics, timing, and hardware thinking.

Nand2Tetris

Nand2Tetris

One of the best bottom-up systems courses ever made.

MIT 6.004 / Computation Structures

MIT

Bridges digital logic, computer architecture, performance, and systems reasoning.

HDLBits

HDLBits

Fastest hands-on path to becoming comfortable with HDL syntax and design patterns.